BSC research in TEXTAROSSA focused on improving the management of parallel applications, introducing the scheduler in the hardware. Scheduling is moved into the hardware by the fast task scheduler component, which was integrated within the RISC-V processors. Specifically, the BSC-developed 30-core RISC-V system demonstrated how hardware Task Scheduling can provide competitive performance with a high number of cores and, incorporates hardware and software optimizations that make this solution even more scalable.
Read more on the participation of BSC in the TEXTAROSSA project.
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