2024, Juan Miguel de Haro Ruiz, et al., Automated parallel execution of distributed task graphs with FPGA clusters, Future Generation Computer Systems, Volume 160, 2024, Pages 808-824, ISSN 0167-739X (open access)
2024, P. Perazzo et al., On hardware acceleration of quantum-resistant FOTA systems in automotive, Computers and Electrical Engineering, Volume 118, Part A, August 2024, 109327 (doi:10.1016/j.compeleceng.2024.109327 (open access)
2024, D. Zoni et al., A Survey on Run-time Power Monitors at the Edge. ACM Comput. Surv. 55, 14s, Article 325 (December 2023), 33 pages. (doi:10.1145/3593044, open access).
2023, L. Morais et al., Enabling HW-based Task Scheduling in Large Multicore Architectures, in IEEE Transactions on Computers, 2023. (doi:10.1109/TC.2023.3323781)
2023, S. D. Matteo et al., VLSI Design and FPGA Implementation of an NTT Hardware Accelerator for Homomorphic SEAL-Embedded Library, IEEE Access, vol. 11, pp. 72498-72508, 2023 (doi:10.1109/ACCESS.2023.3295245 – open access).
2023, M. Bernaschi, et al. A Multi-GPU Aggregation-Based AMG Preconditioner for Iterative Linear Solvers. IEEE Transactions on Parallel and Distributed Systems, vol. 34, no. 8, August 2023. (doi:10.1109/TPDS.2023.3287238, open access).
2022, D. Zoni, et al. Cost-effective fixed-point hardware support for RISC-V embedded systems. Journal of Systems Architecture, Volume 126, May 2022, 102476. (doi:10.1016/j.sysarc.2022.102476, open access)
2022, G. Agosta, et al. Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach. In Microprocessors and Microsystems, 104679. (doi:10.1016/j.micpro.2022.104679, open access)
2022, R. Ammendola, et al. Progress report on the online processing upgrade at the NA62 experiment. Journal of Instrumentation, Volume 17, April 2022. (doi:10.1088/1748-0221/17/04/C04002, open access)
2021, M. Cococcioni, et al. A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications. IEEE Transactions on Emerging Topics in Computing, In press. (doi:10.1109/TETC.2021.3120538, open access)
Conference papers
2024, A. Filgueras, et al., The TEXTAROSSA Project: Cool all the Way Down to the Hardware, Proc. of the 27th Euromicro International Conference on Digital System Design (DSD). (doi).
2024, H. Tayeb et al., Dynamic Tasks Scheduler with Multiple Priority-based Trees on Heterogeneous Computing Systems, IEEE Heterogeneity in Computing Workshop (HCW’24), IPDPS 2024. (open access).
2023, F. Reghenzani et al., Mixed-criticality with integer multiple WCETs and dropping relations: new scheduling challenges , Proceedings of the 28th Asia and South Pacific Design Automation Conference. (doi, open access).
2023, D. Cattaneo et al., Mixed Precision in Heterogeneous Parallel Computing Platforms via Delayed Code Analysis, Springer Embedded Computer Systems: Architectures, Modeling, and Simulation. (doi, open access).
2023, A. Filgueras, et al. Improving performance of hpc kernels on fpgas using high-level resource management. IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2023.
2023, A. Filgueras, et al. FPGA Framework Improvements for HPC Applications. 2023 International Conference on Field Programmable Technology (ICFPT). IEEE, 2023.
2023, A. Ottimo et al. “FSP: a framework for data stream processing applications targeting FPGAs.” 2023 31st Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP). IEEE, 2023.
2023, W. Fornaciari et al., Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC Systems, 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6 (doi:10.23919/DATE56975.2023.10137092, open access).
2023, A. Ghiassi et al., Robust Learning via Golden Symmetric Loss of (un)Trusted Labels, SDM ’23: SIAM International Conference on Data Mining, pp. 568–576 (doi:10.1137/1.9781611977653.ch64, open access).
2023, A. Galimberti et al., An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE, 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms. Open Access Series in Informatics (OASIcs), Volume 107, pp. 4:1-4:12, Schloss Dagstuhl – Leibniz-Zentrum für Informatik (2023)
(doi:10.4230/OASIcs.PARMA-DITAM.2023.4, open access).
2023, O. Beaumont et al., Data Distribution Schemes for Dense Linear Algebra Factorizations on Any Number of Nodes, IEEE International Parallel & Distributed Processing Symposium, In publishing (open access)
2023, P. D’Ambra, F. Durastante, S. M. Ferdous, M. Halappanavar, S. Filippone, A.Pothen, AMG Preconditioners based on Parallel Hybrid Coarsening and Multi-objective Graph Matching, Proc. of the 31th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP), 2023. (doi, open access)
2023, M. Danelutto, et al., FastFlow targeting FPGAs, In Publishing, PDP 2023 – 31st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing. March 1-3, Naples, Italy (doi, open access)
2022, A. Galimberti et al., FPGA implementation of BIKE for quantum-resistant TLS, 25th IEEE Euromicro Conference on Digital System Design (DSD) (doi:10.1109/dsd57027.2022.00078, open access).
2022, F. Reghenzani et al., A Mixed-Criticality Approach to Fault Tolerance: Integrating Schedulability and Failure Requirements, 2022 IEEE 28th Real-Time and Embedded Technology and Applications Symposium (RTAS) (doi:10.1109/rtas54340.2022.00011, open access).
2022, G. Sansone, et al. Experiments on Speeding Up the Recursive Fast Fourier Transform by using AVX-512 SIMD instructions. In Publishing, ApplePies’22 – International Conference on Applications in Electronics Pervading Industry, Environment and Society. (open access)
2022, G. Montanaro, et al. Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators, 2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Glasgow, United Kingdom, 2022, pp. 1-4. (doi:10.1109/ICECS202256217.2022.9970992, open access)
2022, M. Cococcioni, et al. Small Reals Representations for Deep Learning at the Edge: A Comparison. Conference on Next Generation Arithmetic CoNGA 2022 pp 117-133. (doi:10.1007/978-3-031-09779-9_8, open access)
2022, M. Cococcioni, et al. Experimental Results of Vectorized Posit-Based DNNs on a Real ARM SVE High Performance Computing Machine. ApplePies 2021: Applications in Electronics Pervading Industry, Environment and Society pp 61-68. (doi:10.1007/978-3-030-95498-7_9, open access)
2022, H. Tayeb, et al. MulTreePrio: Scheduling taskbased applications for heterogeneous computing systems. COMPAS 2022 – Conférence francophone
d’informatique en Parallélisme, Architecture et Système, Jul 2022, Amiens, France. (available online)
2022, D. Galli, et al. On the Effectiveness of True Random Number Generators Implemented on FPGAs. In Lecture Notes in Computer Science book series (LNCS, volume 13511), Springer. (doi:10.1007/978-3-031-15074-6_20, open access)
2022, A. Galimberti, et al. On the use of hardware accelerators in QC-MDPC code-based cryptography. In Proceedings of the 19th ACM International Conference on Computing Frontiers (CF ’22). Association for Computing Machinery, New York, NY, USA, 193–194. (doi:10.1145/3528416.3530243, open access)
2022, D. Cattaneo, et al. Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time. In Third Workshop on Next Generation Real-Time Embedded Systems (NG-RES 2022), Schloss Dagstuhl–Leibniz-Zentrum für Informatik. (doi:10.4230/OASIcs.NG-RES.2022.4 open access)
2022, W. Fornaciari, et al. The TEXTAROSSA Approach to Thermal Control of Future HPC Systems. In 2022 SAMOS Conference. July 2022. Lecture Notes in Computer Science, vol 13511. Springer, Cham. (doi:10.1007/978-3-031-15074-6_27, open access)
2021, M. Aldinucci, et al. The Italian research on HPC key technologies across EuroHPC. In ACM Computing Frontiers, Virtual Conference, May 2021. (doi:10.1145/3457388.3458508, open access)
2021, G. Agosta, et al. TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale. In 2021 24th Euromicro Conference on Digital System Design (DSD) (pp. 286-294). IEEE. (doi:10.1109/DSD53832.2021.00051, open access)
Presentations
2022, P. D’Ambra, et al. AMG Preconditioners for Computational and Data Science at Extreme Scale, Calcolo Scientifico e Modelli Matematici, Rome, April 8, 2022 (open access).
2022, L. Morais et al., Task scheduling sensitivity to L1 cache settings on an area-constrained 32-core RISC-V processor, 9th BSC Doctoral Symposium, May 2022 (link)
2022, A. Filgueras et al., Improving resource usage in large FPGA accelerators, 9th BSC Doctoral Symposium, May 2022 (link)
2022, M. Bernaschi et al. BootCMatchGX: a scalable iterative linear solver for multi-GPU systems. LN HPCKTT General Assembly and 3rd Italian Workshop on HPC, Turin, Italy. September 2022.
2022, W. Fornaciari. Design of secure power monitors for accelerators, by exploiting ML techniques, in the Euro-HPC TEXTAROSSA project. SCADL WS, Co-located with IPDPS 2022. June 2022.
2022, G. Zummo. Innovative Two-Phase Cooling Solutions for the Exascale Computing Systems. ISC High Performance 2022. May 2022. Slides
2022, A. Lonardo. TEXTAROSSA presentation at the annual INFN Workshop on Computing. May 2022
2022, F. Simula. Distributed and Plastic Spiking Neural Network model of the brain cortex behavior. PSNC textarossa Internal Seminars Series. February 2022.
2021, P. D’Ambra, et al. Algebraic MultiGrid Preconditioners for Sparse Linear Solvers at Extreme Scales on Hybrid Architectures, EuroCC seminar series, July 2021 – CaSToRC: HPC National Competence Center in Cyprus. (slides)
2021, P. D’Ambra, et al. Scalable preconditioners for Computational Science at extreme scale, 13th International Conference on Large-Scale Scientific Computations, Sozopol (BG), June 9, 2021. (open access)
2023, N. Neves et al., An FPGA-based platform to evaluate Posit arithmetic in next-generation processors, ISC High Performance 2023 (link).
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