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ByTEXTAROSSA Project

The TEXTAROSSA Co-Design Approach

Motivation

Supercomputing offers access to enormous amounts of computational power that are needed by many applications in different scientific and industrial sectors. Public services such as weather predictions require such capabilities, as do critical industries like Oil \& Gas (for fuel deposit discovery) and Pharmaceutical (for drug design). Scientific discoveries in fields such as quantum physics or high energy physics are also made possible by supercomputers.

However, increasingly powerful supercomputers are hitting a ceiling imposed by the ability to provide (and sustain) electrical power through the grid. To avoid this limitation, supercomputing hardware designers need to rely on systems that are less power-hungry, but more difficult for application designers to effectively use, due to characteristics such as heterogeneity (that is, the use of processing elements different from the typical “processor” that is commonly found also in laptop and desktop personal computers) and reconfigurability (that is, the use of systems whose functions are programmable at the hardware rather than software level).

TEXTAROSSA Contributions

TEXTAROSSA aims at making the advantages of reconfigurable hardware and associated technical advances available to application developers by means of a co-design approach.
Whereas in standard supercomputing application design, the hardware is given, and the application developer works only at creating the software application, in co-design, hardware and software are designed together, at least in part.

TEXTAROSSA will leverage co-design, which was first developed in the context of embedded systems, through a new Integrated Development Vehicle, a hardware-software platform for supercomputing including reconfigurable hardware elements. TEXTAROSSA aims at providing tools that will help the application developer in designing and implementing the application on this type of platform, semi-automatically performing the tasks of deciding which activities will be performed on the reconfigurable hardware, and producing optimized hardware accelerators for those activities.