Finding novel programming models to better use complex and heterogeneous hardware has been an active research topic for decades. The objectives are to help developers parallelize their applications and increase the efficiency of the resulting applications. Among the successful approaches, the task-based method demonstrated a significant potential.
In this model, a developer splits its program into tasks connected by dependencies, which can usually be represented by a direct acyclic graph. A runtime system is then in charge of executing the task-graph by distributing the tasks over the processing units while ensuring a coherent execution. It can use advanced scheduling strategies that attempt to reduce the makespan or energy consumption, keep the processing units busy, and relieve developers by moving the data when needed.
StarPU is such a runtime system that was developed at Inria since 2009. It targets users with knowledge in HPC and has been successfully used to parallelize a dozen different numerical methods: dense/sparse linear algebra solvers, FMM, BEM solvers, H-matrix solvers, and seismic simulations, among others. In most of these applications, both CPUs and GPUs are used jointly. As such, StarPU is the perfect tool to use to study new technologies and features that will be developed in the Textarossa project through the task-based method.
More precisely, we will study the use of FPGAs in the task-based method and examine their complementarity to the classical HPC devices. At a high level, any existing task-based application can quickly use FPGAs by simply providing some alternative implementations of the tasks. At the runtime system level, an FPGA is nothing more than another type of device accelerator. Consequently, the challenges will come more from the task scheduling and optimization of the energy consumption. This is why we will provide a new scheduling strategy to tackle both aspects that we will validate on two existing StarPU-based applications: ScalFMM and Chameleon.
Leading Partner: INRIA